1. Field of the Invention
This invention relates to minimizing the area of a binary orthogonality checker implemented in static CMOS circuits.
2. Description of Background
This invention relates to minimizing the area of a binary orthogonality checker implemented in static CMOS circuits. Binary orthogonality checkers are used in static CMOS logic to check the control inputs to an orthogonal selector, ensuring there is no data collision between inputs. The checker guarantees that no more than one input to the checker has a true logical value during any comparison cycle. Since the primary purpose of the circuit is a checker, the primary concern for the circuit is to reduce the area the checker uses to complete the function. Within IBM, orthogonality checkers compared each combination of inputs with an AND gate, and then ORed all the outputs (see FIG. 1.) Thus as described in IBM Patent U.S. Pat. Nos. 5,996,040 and 6,038,626 an orthogonality checker was employed in a scalable selector system for controlling data transfers and routing in a data processing system, comprising a plurality of input data buses coupled to a multiple-bit, multiple bus selector having data, data valid, and an orthogonality check outputs and having multiple data input bus ports coupled for receipt of signal from said plurality of input data buses. The system of U.S. Pat. No. 5,996,040 used a multiplicity of said input data buses provide input controls to said multiple-bit, a multiple bus selector to produce a single output data bus signal on a data output bus, and a data valid signal as a control output. The orthogonality check signal controlled data routing logic to allow dataflow to be connected and reconnected without change to control logic. As will be described, for a generalized N input checker completed with a library of gates the solution grows by the squared number for N gates, and thus takes N squared area to implement. As the size of a prior art orthogonality checker grows with the square of the number of inputs, orthogonality checkers with a small number of inputs have a small size. It would be desirable to have a hierarchical checking structure that could be implemented with a smaller area, as well as one which had a smaller logic growth rate as the number of gates increased.